Publications

Conference Proceedings

  • Zero-Cost Proxies for Lightweight NAS [PDF]
    Mohamed S. Abdelfattah, Abhinav Mehrotra, Łukasz Dudziak, Nicholas D. Lane
    International Conference on Learning Representations (ICLR), May 2021.

  • NAS-Bench-ASR: Reproducible Neural Architecture Search for Speech Recognition [PDF]
    Abhinav Mehrotra, Alberto Gil C. P. Ramos, Sourav Bhattacharya, Łukasz Dudziak, Ravichander Vipperla, Thomas Chau, Mohamed S. Abdelfattah, Samin Ishtiaq, Nicholas D. Lane
    International Conference on Learning Representations (ICLR), May 2021.

  • BRP-NAS: Prediction-based NAS using GCNs [ARXIV]
    Łukasz Dudziak, Thomas Chau, Mohamed S. Abdelfattah, Royson Lee, Hyeji Kim, Nicholas D. Lane
    Neural Information Processing Systems (NeurIPS), Dec. 2020.

  • Iterative Compression of End-to-End ASR Model Using Reinforcement learning [ARXIV]
    Abhinav Mehrotra, Łukasz Dudziak, Jinsu Yeo, Younyoon Lee, Ravichander Vipperla, Mohamed S. Abdelfattah, Sangjeong Lee, Daehyun Kim, Nicholas D. Lane
    Conference of the International Speech Communication Association (INTERSPEECH), Oct. 2020.

  • Journey Towards Tiny Perceptual Super-Resolution [ARXIV]
    Royson Lee, Łukasz Dudziak, Mohamed S. Abdelfattah, Hyeji Kim, Stylianos Veneris, Hongkai Wen, Nicholas D. Lane
    European Conference on Computer Vision (ECCV), Aug. 2020.

  • Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator [ARXIV]
    Mohamed S. Abdelfattah, Łukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane
    Design Automation Conference (DAC), July 2020.

  • ShrinkML: End-to-End ASR Model Compression Using Reinforcement Learning [PDF]
    Łukasz Dudziak, Mohamed S. Abdelfattah, Ravichander Vipperla, Stefanos Laskaridis, Nicholas D. Lane
    Conference of the International Speech Communication Association (INTERSPEECH), Sep. 2019.

  • DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration [PDF]
    Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O’Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling and Gordon R. Chiu
    International Conference on Field-Programmable Logic and Applications (FPL), Sep. 2018.

  • Harnessing Numerical Flexibility for Deep Learning on FPGAs [PDF]
    Andrew C. Ling, Mohamed S. Abdelfattah, Shane O’Connell, Andrew Bitar, David Han, Roberto Dicecco, Suchit Subhaschandra, Chris N Johnson, Dmitry Denisenko, Josh Fender, Gordon R. Chiu
    International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Jun. 2018.

  • Flexibility: FPGAs and CAD in Deep Learning Acceleration [PDF]
    Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah
    International Symposium on Physical Design (ISPD), Mar. 2018.

  • LYNX: CAD for FPGA-based networks-on-chip [PDF]
    Mohamed S. Abdelfattah, Vaughn Betz
    International Conference on Field-Programmable Logic and Applications (FPL), Sep. 2016.
    Nominated for the Michel Servit Best Paper Award

  • Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA [PDF]
    Andrew Bitar, Mohamed S. Abdelfattah, Vaughn Betz
    International Conference on Field-Programmable Technology (FPT), Dec. 2015.

  • Design and simulation tools for Embedded NOCs on FPGAs [PDF]
    Mohamed S. Abdelfattah, Andrew Bitar, Ange Yaghi, Vaughn Betz
    International Conference on Field-Programmable Logic and Applications (FPL), Sep. 2015.

  • Take the highway: Design for embedded NoCs on FPGAs [PDF]
    Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz
    International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2015.
    Best Paper Award

  • Gzip on a chip: High performance lossless data compression on fpgas using opencl [PDF]
    Mohamed S. Abdelfattah, Andrei Hagiescu, Desh Singh
    International Workshop on OpenCL (IWOCL), May 2014.

  • Augmenting FPGAs with Embedded Networks on Chip [PDF]
    Mohamed S. Abdelfattah, Vaughn Betz
    Workshop on the Intersection of Computer Architecture and Reconfigurable Logic (CARL), May 2013.

  • The Power of Communication: Energy-Efficient NoCs for FPGAs [PDF]
    Mohamed S. Abdelfattah, Vaughn Betz
    International Conference on Field-Programmable Logic and Applications (FPL), Sep. 2013.
    Stamatis Vassiliadis Best Paper Award

  • Design tradeoffs for hard and soft FPGA-based Networks-on-Chip [PDF]
    Mohamed S. Abdelfattah, Vaughn Betz
    International Conference on Field-Programmable Technology (FPT), Dec. 2012.

  • Transparent Structural Online Test for Reconfigurable Systems [PDF]
    Mohamed S. Abdelfattah, Lars Bauer, Claus Braun, Michael E Imhof, Michael A Kochte, Hongyan Zhang, J\örg Henkel, Hans-Joachim Wunderlich
    International Symposium on On-Line Testing and Robust System Design (IOLTS), Jun. 2012.

  • 2.2 GHz LC VCO for RFID on a 0.5-$\mu$m digital gate-array designed for ultra-thin silicon substrates [PDF]
    Mohamed S. Abdelfattah, Damir Ferenci, Markus Gr\özing, Manfred Berroth, Cor Scherjon, Joachim Burghartz
    German Microwave Conference (GeMiC), Mar. 2011.

  • Design of a RF Transmitter for RFID Tags in a New Technology with Ultra Thin Silicon Substrates [PDF]
    Mohamed S. Abdelfattah, Damir Ferenci, Markus Gr\özing, Manfred Berroth, Cor Scherjon, Joachim N Burghartz
    Workshop on Circuit Design and Digital Signal Processing (ProRISC), Aug. 2009.

Journal Articles

  • Design and applications for embedded networks-on-chip on FPGAs [PDF]
    Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz
    IEEE Transactions on Computers (TCOMP), Oct. 2016.

  • Power analysis of embedded NoCs on FPGAs and comparison with custom buses [PDF]
    Mohamed S. Abdelfattah, Vaughn Betz
    IEEE Transactions on Very Large-Scale Integration Systems (TVLSI), Feb. 2015.

  • Networks-on-Chip for FPGAs: Hard, Soft or Mixed? [PDF]
    Mohamed S. Abdelfattah, Vaughn Betz
    ACM Transactions on Reconfigurable Technology and Systems (TRETS), Aug. 2014.

  • The Case for Embedded Networks-on-Chip on FPGAs [PDF]
    Mohamed S. Abdelfattah, Vaughn Betz
    IEEE Micro Magazine, Feb. 2014.

Book Chapters

  • Embedded Networks-on-Chip for FPGAs [PDF]
    Mohamed S. Abdelfattah, Vaughn Betz
    Reconfigurable Logic: Architecture, Tools and Applications, Jan. 2015.

Patent Applications

  • Method and Apparatus for Neural Architecture Search
    Mohamed S. Abdelfattah, Łukasz Dudziak, Abhinav Mehrotra
    Application Number: UK2015231.0, Sep. 2020.

  • Method and Apparatus for Analysing Neural Network Performance
    Thomas Chau, Łukasz Dudziak, Mohamed S. Abdelfattah, Royson Lee, Nicholas D. Lane
    Application Number: UK20199106.4, Sep. 2020.

  • Method for Designing Accelerator Hardware [PDF]
    Mohamed S. Abdelfattah, Łukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Sourav Battacharaya
    Application Number: UK1913353.7, Sep. 2019.

  • Field Programmable Gate-Array with Embedded Network-on-Chip Hardware and Design Flow [PDF]
    Mohamed S. Abdelfattah, Vaughn Betz
    Application Number: US14060253, Apr. 2015.

Theses

  • PhD: Embedded Networks on Chip for Field-Programmable Gate Arrays [PDF]

  • MSc: Evaluation of advanced techniques for structural FPGA self-test [PDF]

  • BSc: Design of a RF Transmitter for RFID Tags in a New Technology with Ultra Thin Silicon Substrates [PDF]